IC devices having TSVS including protruding tips having IMC blocking tip ends

ABSTRACT

A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ≧25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

FIELD

Disclosed embodiments relate to integrated circuits (ICs) including TSVICs that include protruding TSV tips.

BACKGROUND

As known in the art, through-substrate vias (referred to herein asTSVs), which are commonly referred to as through-silicon vias, arevertical electrical connections that extend the full thickness of thewafer from one of the electrically conductive levels formed on thetopside semiconductor surface of the IC die (e.g., contact level or oneof the BEOL metal interconnect levels) to its bottomside surface. Thevertical electrical paths are significantly shortened relative toconventional wire bonding technology, generally leading to significantlyfaster device operation. In one arrangement, the TSVs terminate on oneside of the IC die referred to herein as a “TSV die” as protruding TSVtips, such as protruding from the bottomside surface of the TSV die. TheTSV die can be bonded face-up or face-down, and can be bonded to fromboth sides to enable formation of stacked IC devices.

The TSV area is often limited because the TSV area cannot generally beincreased due to area restrictions on the TSV die and/or TSV impartedstress on one or more layers on the TSV die. For a conventional soldermediated joint involving a TSV tip, since solder has a relatively lowelectromigration (EM) current limit (e.g., typical EM-limited currentdensity for conventional solder is around 10⁴ A/cm², about one hundredtimes lower than that of Cu or Al), the EM current density through theTSV-comprising joint is generally limited by the interfacial areabetween the TSV tip and the overlying solder on the TSV tips.

Moreover, applied to stacked die assemblies, TSV areas that aresignificantly smaller as compared to the adjoining bond pads or bondingfeatures on a top IC die bonded to the TSV die generally limit theoverall EM performance for the stacked die assembly. Conventionalsolutions to this EM problem involve addition of a patterned metal padover the TSV tip enabled by adding an additional backside metal step, orby formation of additional TSVs (to provide TSVs in parallel) to reducethe current in selected TSVs on the TSV die.

SUMMARY

Disclosed embodiments describe TSV die having protruding TSV tips thatinclude distal tip ends that can solve the EM problem described abovewithout the added cost and cycle time of adding a patterned metal padover the TSV tips or the die area penalty associated with includingadditional TSVs in parallel. The Inventor has also recognized thatdisclosed embodiments avoid or at least significantly delay theconsumption of the inner metal core of the TSV from forming aninter-metallic compound (IMC) with overlying Sn-based solder in the caseof solder mediated joints, which helps prevent IMC-induced cracking ofthe outer dielectric sleeve that can result in failures (e.g., leakageor shorts) on the TSV die, especially near the point where theprotruding TSV tip exits the bottomside of the die.

The distal tip ends comprise a first metal layer including a first metalother than solder covering an exposed portion of the protruding TSV tipsand a second metal layer including a second metal other than solder thatis different from the first metal on the first metal layer. The firstmetal layer together with the second metal layer provides a bulbousdistal tip end that covers a portion of the TSV sidewalls and a topmostsurface of the outer dielectric sleeve, and provides a cross sectionalarea that is ≧25% more as compared to a cross sectional area of theprotruding TSV tip below the bulbous distal tip end.

One disclosed embodiment is a method of forming TSV die that includesplating a first metal layer exclusive of solder on a distal portion of aprotruding TSV tip of a TSV that comprises an outer dielectric sleeveand an inner metal core, and plating a second metal layer exclusive ofsolder that is different from the first metal layer on the first metallayer. The first metal layer together with the second metal layerprovides a bulbous distal tip end for the protruding TSV tip that coversa portion of the TSV sidewalls and a topmost surface of the outerdielectric sleeve, and provides a cross sectional area that is ≧25% moreas compared to a cross sectional area of the protruding TSV tip belowthe bulbous distal tip end.

The method can further comprise depositing a dielectric passivationlayer on the bottomside surface of a wafer that includes a plurality ofTSV die including over the protruding TSV tips. The passivation layercan then be etched (e.g., dry etched) to reveal a distal portion of theprotruding TSV tips including an exposed portion of the inner metalcores of the TSVs. The bulbous distal tip ends can then be formed on thedistal portion of the protruding TSV tips. The forming of bulbous distaltip ends can comprise selectively electrolessly plating the first andsecond metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a flow chart that shows steps in an exemplary method offorming TSV die, according to an embodiment of the invention.

FIG. 1B is a flow chart that shows steps in an exemplary method offorming TSV die, according to another embodiment of the invention.

FIG. 2A is a simplified cross sectional depiction of a TSV diecomprising a TSV having a bulbous distal tip end, according to anembodiment of the invention.

FIG. 2B is a simplified cross sectional depiction of a TSV diecomprising a TSV having a bulbous distal tip end, according to anotherembodiment of the invention.

FIG. 3 is a simplified cross sectional depiction of a TSV die comprisinga TSV having a bulbous distal tip end related to the embodiment shown inFIG. 2A, modified so that the outer dielectric TSV sleeve extends alongthe sidewalls of the protruding TSV tips for a distance less than alength of the protruding TSV tips, according to another embodiment ofthe invention.

FIG. 4 is a simplified cross sectional depiction of a stacked IC devicecomprising a TSV die comprising a TSV having a bulbous distal TSV tipend, and a second IC die having a plurality of protruding bondingfeatures with a protruding bonding feature shown joined at a reflowedsolder joint to the protruding TSV tip, according to an embodiment ofthe invention.

DETAILED DESCRIPTION

Disclosed embodiments in this Disclosure are described with reference tothe attached figures, wherein like reference numerals are usedthroughout the figures to designate similar or equivalent elements. Thefigures are not drawn to scale and they are provided merely toillustrate the disclosed embodiments. Several aspects are describedbelow with reference to example applications for illustration. It shouldbe understood that numerous specific details, relationships, and methodsare set forth to provide a full understanding of the disclosedembodiments. One having ordinary skill in the relevant art, however,will readily recognize that the subject matter disclosed herein can bepracticed without one or more of the specific details or with othermethods. In other instances, well-known structures or operations are notshown in detail to avoid obscuring structures or operations that are notwell-known. This Disclosure is not limited by the illustrated orderingof acts or events, as some acts may occur in different orders and/orconcurrently with other acts or events. Furthermore, not all illustratedacts or events are required to implement a methodology in accordancewith this Disclosure.

Notwithstanding that the numerical ranges and parameters setting forththe broad scope of this Disclosure are approximations, the numericalvalues set forth in the specific examples are reported as precisely aspossible. Any numerical value, however, inherently contains certainerrors necessarily resulting from the standard deviation found in theirrespective testing measurements. Moreover, all ranges disclosed hereinare to be understood to encompass any and all sub-ranges subsumedtherein. For example, a range of “less than 10” can include any and allsub-ranges between (and including) the minimum value of zero and themaximum value of 10, that is, any and all sub-ranges having a minimumvalue of equal to or greater than zero and a maximum value of equal toor less than 10, e.g., 1 to 5.

FIG. 1A is a flow chart that shows steps in an exemplary method 100 offorming TSV die, according to an embodiment of the invention. Step 101comprises providing a wafer comprising a plurality of TSV die. The TSVdie includes at least one, and generally a plurality of TSVs thatcomprise an inner metal core and an outer dielectric sleeve that extendsthe full thickness of the die from the topside semiconductor surface(generally coupled to the contact level or one of the BEOL metal layers(e.g., M1, M2, etc.)) to protruding TSV tips that emerge from thebottomside surface of the TSV die. The inner metal core can comprise Cuin one embodiment. Other electrically conductive materials can be usedfor the inner metal core. In one embodiment the TSV diameter is ≦12 μm,such as 8.5 to 10 μm in one particular embodiment.

The outer dielectric sleeve can comprise materials such as siliconoxide, silicon nitride, phosphorus-doped silicate glass (PSG), siliconoxynitride, or certain CVD polymers (e.g., parylene). The outerdielectric sleeve is typically 0.2 to 5 μm thick. In the case of copperand certain other metals for the inner metal core, a metal diffusionbarrier layer referred to herein as a “TSV barrier” is generally added,such as a refractory metal or a refractory metal nitride. For example,TSV barrier materials can include materials including Ta, W, Mo, Ti,TiW, TiN, TaN, WN, TiSiN or TaSiN, which can be deposited by physicalvapor deposition (PVD) or chemical vapor deposition (CVD). The TSVbarrier is typically 100-500 A thick. The distal portion of the TSV tipincludes an exposed (i.e., dielectric sleeve free) area that at leastexposes the topmost surface of the inner metal core to allow electricalcontact thereto.

Step 102 comprises plating a first metal layer exclusive of solder on adistal portion of a protruding TSV tip. The first metal layer forms anelectrical contact with at least the topmost surface of the inner metalcore. The first metal layer is generally 1 to 4 μm thick. The firstmetal layer provides both an IMC block and current spreader function.The first metal layer can comprise materials including Ni, Pd, Co, Cr,Rh, NiP, NiB, CoWP or CoP, for example. The plating can compriseelectroless plating. As known in the art of plating, electroless platingis a selective deposition process that only deposits on certain exposedmetal or semiconductor surfaces, not on dielectrics such as polymers,oxides and nitrides, and thus does not involve lithography to generate apattern or an etching step to remove the excess deposited material. Inanother embodiment, electroplating can be used by building a patternedlayer using lithography so that an electroplated pad can be created overthe TSV tip to localize the deposition to the tip region using anelectroplating process.

Step 103 comprises plating a second metal layer exclusive of solder thatis different from the first metal layer on the first metal layer. Theplating can comprise electroless plating. As with step 102 describedabove, the plating can comprise electroplating. The first metal layertogether with the second metal layer provide a bulbous distal tip endfor the protruding TSV tip. The bulbous distal tip end covers a portionof the TSV sidewalls and a topmost surface of the outer dielectricsleeve, and provides a maximum cross sectional area that is ≧25% more ascompared to a cross sectional area of the protruding TSV tip below thebulbous distal tip end. In another embodiment, the bulbous distal tipend has a maximum cross sectional area that is ≧40% more as compared toa cross sectional area of the protruding TSV tip below the bulbousdistal tip end. For example the TSV tip diameter can be 6 to 10 μm, andthe combined thickness of the first and second metal layers can be 1 to5 μm thick.

For electroless processes, which as known in the art are characterizedby isotropic deposition patterns beginning on certain metal (e.g., Cu)or semiconductor surfaces, the deposited thickness in dimensionsperpendicular to the length dimension of the TSV tip is typically 70% to85% of the deposited thickness in the length dimension of the TSV tip.Accordingly, a 4 μm thick deposition thickness provides about a 6 μmincrease in the width dimension of the TSV.

In a first particular embodiment, the first metal layer comprises Ni andthe second metal layer comprises Cu, Pt, Pd or Au. For example, the Nican be 1 to 4 μm thick, and the second metal layer can comprise 2 to 5μm thick Cu. Ni provides an IMC block, while the second metal embodiedas a Cu layer both contributes to subsequent conversion of the solderinto a Cu_(x)Sn_(y) IMC and delays the full conversion of Ni in thefirst metal layer to IMC, thereby extending the EM capability.

By forming the bulbous tip ends, the effective tip area is increasedsignificantly, which reduces the current density at the interfacebetween the TSV tip and the solder. Moreover, the bulbous tip endblocks/delays IMC formation reaction into the TSV tip. The bulbousdistal tip also retards the consumption of the TSV inner metal core(e.g., Cu) from forming IMC with overlying Sn-based solder.

In a second particular embodiment, the first metal layer comprises Niand the second metal layer comprises Pd. In this second particularembodiment the Pd can be 0.2 to 0.6 μm thick. An immersion Au layer canbe deposited on the Pd or other second metal layer in the secondparticular embodiment to improve solder wetting. The Au layer can be 200to 500 A thick. Pd can provide a block to prevent Au diffusion throughto the TSV tip and can provide a block to prevent P (e.g., fromunderlying NiP) from corroding the Au.

FIG. 1B is a flow chart that shows steps in an exemplary method 150 offorming TSV die, according to another embodiment of the invention. Step151 comprises providing a wafer comprising a plurality of TSV die, whereeach TSV die has a topside semiconductor surface including activecircuitry and a bottomside surface, and a plurality of TSVs. The TSVscomprise an inner metal core and an outer dielectric sleeve that extendsthe full thickness of the die from the topside semiconductor surface(generally coupled to the contact level or one of the BEOL metal layers(e.g., M1, M2, etc.) to protruding TSV tips that emerge from thebottomside surface of the TSV die. The TSV tips include sidewalls.

Step 152 comprises depositing a dielectric passivation layer on thebottomside surface of the wafer including over the protruding TSV tips.In one embodiment the passivation layer is deposited using a spin-onprocess. However, other deposition processes may be used.

Step 153 comprises etching the passivation layer to reveal a distalportion of the protruding TSV tips including exposing a portion of theinner metal core, wherein after the etching the passivation layercontinues to cover the bottomside surface of the wafer lateral to theprotruding TSV tips and a portion of the sidewalls. Dry etching can beused for this step. Some wet etch process may also be suitable. Forexample, one exemplary wet etch process coats the TSV tips with adielectric polymer that encapsulates the TSV tips, and then a portion ofthe dielectric polymer is removed from the TSV tips using a solvent toexpose a distal tip portion of the TSV tips to permit electricalconnection thereto.

In one embodiment step 152 can comprise chemical vapor deposition (CVD)of a dielectric passivation layer comprising silicon nitride or siliconoxynitride, and step 153 can comprise chemical mechanical polishing(CMP) to reveal a distal portion of the protruding TSV tips includingexposing a portion of the inner metal core. In this embodiment the metalplating (steps 154, 155 described below) would grow laterally acrossthis passivation layer.

Step 154 is analogous to step 102 in method 100 and comprises plating afirst metal layer exclusive of solder on a distal portion of aprotruding TSV tip of a TSV. The plating can comprise electrolessplating. Step 155 is analogous to step 103 in method 100 and comprisesplating a second metal layer exclusive of solder that is different fromthe first metal layer on the first metal layer. The plating can compriseelectroless plating. The first metal layer together with the secondmetal layer provide a bulbous distal tip end for the protruding TSV tip.The bulbous distal tip end covers a portion of the TSV sidewalls and atopmost surface of the outer dielectric sleeve, and has a maximum crosssectional area that is ≧25% more as compared to a cross sectional areaof the protruding TSV tip below the bulbous distal tip end.

FIG. 2A is a simplified cross sectional depiction of a TSV die 200comprising at least one TSV 216 having protruding TSV tip 217 having abulbous distal tip end 217(a), according to an embodiment of theinvention. TSV die 200 comprises a substrate 205 including a topsidesemiconductor surface 207 including active circuitry 209 and abottomside surface 210. The connector 208 shown depicts the couplingbetween the TSV 216 on the topside semiconductor surface 207 to theactive circuitry 209. The TSV 216 comprises an outer dielectric sleeve221 and an inner metal core 220, and a TSV barrier layer 222 between theouter dielectric sleeve 221 and an inner metal core 220. The TSV 216extends from the topside semiconductor surface 207 to protruding TSV tip217 emerging from the bottomside surface 210. The TSV tip includessidewalls having outer dielectric sleeve 221 and barrier layer 222thereon.

A dielectric passivation layer 231 is lateral to the protruding TSV tip217 including on a portion the sidewalls of the protruding TSV tip 217.The passivation layer 231 is absent from the distal portion of theprotruding TSV tip 217 to provide an exposed portion of the inner metalcore 220.

A first metal layer 241 that includes a first metal other than soldercovers the exposed portion the protruding TSV tip 217. A second metallayer 242 including a second metal other than solder that is differentfrom the first metal is on the first metal layer 241. It can be seenthat the first metal layer 241 together with the second metal layer 242provides a bulbous distal tip end 217(a) for the protruding TSV tip 217that covers a portion of the TSV sidewalls and a topmost surface 221(a)of the outer dielectric sleeve 221, and provides a cross sectional areathat is ≧25% more as compared to a cross sectional area of theprotruding TSV tip 217 below the bulbous distal tip end 217(a).

During assembly, reliability testing, and during use, solder used inconventional TSV joints will consume inner metal core (e.g., Cu) fromthe TSV tips when the TSVs lack a metal cap that functions as an IMCbarrier, which can lead to conversion of the TSV inner core metal suchas Cu to an IMC. The Inventors have recognized that IMC formationinduces a volumetric increase that can rupture the surrounding outerdielectric sleeve 221 especially near the point where the protruding TSVtip 217 exits the bottomside surface 210 of the substrate 205. Thebulbous tip ends 217(a) disclosed herein besides reducing the currentdensity at the TSV tip's interface with the solder, as noted aboveblocks/delays IMC formation reaction into the TSV tip. The bulbous tipalso retards the consumption of the TSV inner metal core (e.g., Cu) fromforming IMC with overlying Sn-based solder. FIG. 4 described below showsan exemplary solder joint that couples a TSV tip having a bulbous tipend protruding from a bottomside surface of a TSV die and second IC diehaving a plurality of protruding bonding features.

FIG. 2B is a simplified cross sectional depiction of a TSV die 250comprising at least one TSV having a bulbous distal tip end, accordingto another embodiment of the invention. The bulbous tip end 217(b) shownin FIG. 2B comprises an optional third metal layer 243, a second metallayer 242 and a first metal layer 241. In this embodiment the firstmetal layer 241 can comprise Ni (e.g., 1 to 4 μm thick), the secondmetal layer 242 can comprise Pd (e.g., 0.2 to 0.6 μm thick) and thethird metal layer 243 can comprise Au (e.g., 200 to 500 A thick). Asnoted above Pd can provide a block for possible Au diffusion and canalso provide a block against possible corrosion of the Au by P fromunderlying NiP.

FIG. 3 is a simplified cross sectional depiction of a TSV die 300comprising a TSV 216 having a bulbous distal tip end 217(a) related tothe embodiment shown in FIG. 2A, modified so that the outer dielectricTSV sleeve 221 extends along the sidewall of the protruding TSV tip 217for a distance less than a length of the protruding TSV tips 217. Thisdistance, referred to herein as an intermediate distance (Di), can be:

-   -   ⅓ a length of the protruding TSV tip<Di<the length of the        protruding TSV tip−1 μm.        An exemplary method for forming such TSV tips having outer        dielectric TSV sleeves 221 that extend along the sidewall of the        protruding TSV tip 217 for a distance less than a length of the        protruding TSV tips 217 can be found in commonly assigned Pub.        U.S. Pat. App. No. 20090278238 to Bonifield, et al.

FIG. 4 is a simplified cross sectional depiction of a stacked IC device400 comprising a first TSV die 200 (shown in FIG. 2A as described above)comprising a TSV 216 having a bulbous distal TSV tip end 217(a), and asecond IC die 420 having a plurality of protruding bonding features witha single bonding feature (e.g., copper pad) 425 on a bond pad 422 shownjoined at a reflowed solder (e.g., electrolytic SnAg 2.5 wt. % solder)joint 435 to the bulbous tip ends 217(a) of the TSV die 200. IMC 426(e.g., Cu_(x)Sn_(y)) is shown on the bonding feature 425 resulting fromthe solder reflow processing.

The third metal layer 243 shown in FIG. 2B is not shown in FIG. 4 sinceit generally completely dissolves and thus fully diffuses into thesolder during solder reflow to become included in the reflowed solderjoint 435. In addition, another IMC layer 426′ is formed between solderin the solder joint 435 and the second metal layer 242, such as a Nisecond metal layer. In the case the second metal layer 242 comprises Ni,IMC layer 426′ will be much thinner as compared to IMC layer 426 sinceIMC forms at a faster rate between the bond pad 425 when it is Cu and Snas compared to the IMC formation rate between Ni and Sn.

FIG. 4 also shows how disclosed bulbous tip ends solves problem ofhaving to build a patterned metal pad over the TSV tips on the backsideof the wafer or to add additional TSVs to supply sufficient current tonext tier because of EM limitations on the (relatively) smaller TSV tipcross sectional area (e.g., diameter) vs. the adjoining pad 425 bysignificantly increasing the effective area of the distal end of the TSVtip 217.

The active circuitry formed on the topside semiconductor surfacecomprises circuit elements that generally include transistors, diodes,capacitors, and resistors, as well as signal lines and other electricalconductors that interconnect these various circuit elements. Disclosedembodiments can be integrated into a variety of process flows to form avariety of devices and related products. The semiconductor substratesmay include various elements therein and/or layers thereon. These caninclude barrier layers, other dielectric layers, device structures,active elements and passive elements including source regions, drainregions, bit lines, bases, emitters, collectors, conductive lines,conductive vias, etc. Moreover, disclosed embodiments can be used in avariety of processes including bipolar, CMOS, BiCMOS and MEMS.

While various disclosed embodiments have been described above, it shouldbe understood that they have been presented by way of example only, andnot limitation. Numerous changes to the subject matter disclosed hereincan be made in accordance with this Disclosure without departing fromthe spirit or scope of this Disclosure. In addition, while a particularfeature may have been disclosed with respect to only one of severalimplementations, such feature may be combined with one or more otherfeatures of the other implementations as may be desired and advantageousfor any given or particular application.

Thus, the breadth and scope of the subject matter provided in thisDisclosure should not be limited by any of the above explicitlydescribed embodiments. Rather, the scope of this Disclosure should bedefined in accordance with the following claims and their equivalents.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting. As used herein, thesingular forms “a,” “an,” and “the” are intended to include the pluralforms as well, unless the context clearly indicates otherwise.Furthermore, to the extent that the terms “including,” “includes,”“having,” “has,” “with,” or variants thereof are used in either thedetailed description and/or the claims, such terms are intended to beinclusive in a manner similar to the term “comprising.”

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which embodiments of the inventionbelongs. It will be further understood that terms, such as those definedin commonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

1. A method of forming through substrate via (TSV) die, comprising:plating a first metal layer exclusive of solder on a distal portion of aprotruding TSV tip of a TSV that includes sidewalls and comprises anouter dielectric sleeve and an inner metal core, and plating a secondmetal layer exclusive of solder that is different from said first metallayer on said first metal layer, wherein said first metal layer togetherwith said second metal layer provides a bulbous distal tip end for saidprotruding TSV tip that covers a portion of said TSV sidewalls and atopmost surface of said outer dielectric sleeve, said bulbous distal tipend having a cross sectional area that is ≧25% more as compared to across sectional area of said protruding TSV tip below said bulbousdistal tip end.
 2. The method of claim 1, wherein said plating saidfirst metal layer and said plating said second metal layer both compriseselective electroless plating, and wherein said bulbous distal tip endis selectively formed on said distal portion of said protruding TSV tip.3. The method of claim 2: wherein said TSV die is on a wafer comprisinga plurality of said TSV die, and wherein each of said plurality of TSVdie have a topside semiconductor surface including active circuitry anda bottomside surface and including a plurality of said TSVs, whereinsaid plurality of TSVs extend from said active circuitry on said topsidesemiconductor surface to said protruding TSV tips emerging from saidbottomside surface, and wherein said protruding TSV tips includesidewalls, said method further comprising before said selectiveelectroless plating: depositing a passivation layer on said bottomsidesurface of said wafer including over said protruding TSV tips; etchingsaid passivation layer to reveal a distal portion of said protruding TSVtips including exposing a portion of said inner metal core, whereinafter said etching said passivation layer continues to cover saidbottomside surface of said wafer lateral to said protruding TSV tips anda portion of said sidewalls.
 4. The method of claim 3, wherein saiddepositing comprises chemical vapor deposition (CVD), said passivationlayer comprises silicon nitride or silicon oxynitride, and said etchingcomprises chemical mechanical polishing (CMP).
 5. The method of claim 1,wherein said first metal layer comprises Ni, Pd, Co, Cr, Rh, NiP, NiB,CoWP or CoP.
 6. The method of claim 5, wherein said first metal layercomprises Ni and second metal layer comprises Cu.
 7. The method of claim5, wherein said first metal layer comprises Ni and said second metallayer comprises Pd.
 8. The method of claim 7, further comprisingdepositing a Au layer on said second metal layer.
 9. The method of claim1, wherein said outer dielectric sleeve extends along said sidewalls ofsaid protruding TSV tip to an intermediate distance (Di), wherein: ⅓ alength of said protruding TSV tip<Di<said length of said protruding TSVtip−1 μm.